Conventionally, designers designed the various modules of a chip at the gate level by using a schematic capture technique. In contrast, today, the various modules of a chip are designed at the register transfer level (RTL) using hardware description languages (HDL's). Evolutions of hardware description languages (HDLs) and advances in simulation and synthesis technologies for the HDLs have enabled chip designers to design at a higher (resistor transfer) level of abstraction than at the "gate" level.
When designing at the RTL, the designer describes a module in terms of signals which are generated and propagated through combinational modules from one set of registers to another set of registers. HDLs provide a rich set of constructs to describe the functionality of a module at RTL. At this level, the functionality is described by using high level constructs such as concurrent PROCESS blocks with sensitization lists, IF statements, CASE statements, and assignment statements that use logical operators, arithmetic operators, and relational operators. Verilog and VHDL are the most popular HDLs among designers and both are IEEE standards.
Software tools that are used to design hardware that generate modules at the RTL generally must be capable of generating the modules in both Verilog and VHDL. Although both languages model and describe hardware, their syntax is quite different and some functionalities of these two HDLs are non overlapping. Due to the different syntax and varying functionality of these two languages, a significant amount of effort is required to generate the correct syntax. In addition, conventional systems use two separate code generators, one for Verilog and one for VHDL. The use of two generators makes the task of maintaining the system in synchronization difficult.
What is needed is a system and method for (1) generating an RTL design without requiring detailed knowledge of Verilog and VHDL while (2) making software development and maintenance easier.